Getting Started with Vyges: Build Your First Silicon IP Block

Use AI‑assisted development and Vyges conventions to build reusable silicon IP — backed by open‑source tools and CI.

August 11, 2025 • By Shivaram Mysore

🚀 Why This Matters

Vyges brings modern, software-style workflows to silicon IP, enabling reuse, automation, and collaboration like never before. With a GitHub account and an AI-powered IDE, you can start building reusable, verifiable RTL blocks in minutes.

🧰 What You'll Need

  • A GitHub account
  • An AI-enabled IDE like Cursor or GitHub Copilot
  • Basic knowledge of SystemVerilog, VHDL, or cocotb
  • Open-source tools installed (Mac or Linux):
  • verilator
  • icarus verilog
  • yosys
  • python3 with cocotb

🧱 Step 1 — Use the Vyges IP Template

Create a new repository from our open-source template:

➡️ https://github.com/vyges/vyges-ip-template/generate

  1. Click "Use this template"
  2. Name your repo using Vyges conventions (e.g., my-functionality-ip or fft-accelerator-ip)
  3. Set it to Public — this ensures GitHub CI runs for free
  4. Click "Create repository from template"

Important: To avoid namespace collisions, your IP will be recognized as YOUR_GITHUB_USERNAME/my-functionality-ip in the Vyges ecosystem.

Your repo will include:

  • RTL scaffolding
  • cocotb-based testbenches
  • Vanilla GitHub Actions CI configuration
  • vyges-metadata.json template
  • Build instructions
  • Generic reporting scripts in the scripts/ directory

Once created, clone it to your local machine:

git clone https://github.com/YOUR_USERNAME/my-functionality-ip.git

cd my-functionality-ip

✍️ Step 2 — Define the Architecture Using Vyges Conventions

Use Cursor or GitHub Copilot to scaffold designs quickly. Be specific about your IP requirements - the more clarity you provide, the more accurate the design will be.

Pro Tip: The Vyges template includes intelligent AI context files that automatically guide your development. When you open the repository in Cursor or GitHub Copilot, the AI understands Vyges conventions, naming patterns, and best practices - ensuring your IP follows industry standards without manual configuration. This Vyges technology ensures consistent, professional results across all IP development.

Example: Fast Fourier Transform Accelerator

Instead of a generic prompt, use specific requirements and always mention "Vyges Conventions" to keep the AI focused:

Example FFT Accelerator Requirements:

Use Vyges Conventions to create design specification and architecture for a Fast Fourier Transform hardware accelerator with these requirements:

  • Design a hardware accelerator for FFT (length can range from 256 to 4096)
  • Assume 16-bit twiddle factor coefficients and 16-bit input and output data
  • Double buffer the input and output arrays so background data transfer can happen
  • Assume that the accelerator memories for input and output are memory mapped to host processor
  • Performance requirement: one butterfly computation in 6 cycles

Generate the architecture specification, interface definitions, and update the vyges-metadata.json file.

Example: UART Controller

For a UART controller, be specific and maintain focus:

Example UART Controller Requirements:

Use Vyges Conventions to create design specification and architecture for a UART controller with:

  • Configurable baud rates: 9600, 19200, 38400, 57600, 115200
  • 8-bit data width with optional parity
  • FIFO buffers (configurable depth: 16, 32, 64)
  • Interrupt-driven operation with status registers
  • AXI4-Lite interface for register access
  • UART TX/RX with flow control support

This helps generate structured metadata, interface specs, and scaffolded RTL that meets your exact needs.

🔨 Step 3 — Implement RTL & Testbenches

First, review the generated architecture and specifications to ensure they meet your requirements. Check the generated documentation and verify the design approach aligns with your needs.

Then, check the vyges-metadata.json file - it contains valuable information about how the code will be generated, including: - Interface specifications - Parameter definitions - File naming conventions - Tool requirements

AI Context is Already Loaded: Since you're working within the Vyges template directory, Cursor or GitHub Copilot automatically has access to all Vyges conventions, naming patterns, and best practices through the intelligent context files. This Vyges technology prevents the AI from falling back to generic or incorrect patterns.

Now implement the RTL and testbenches:

Prompt your AI IDE (always mention Vyges Conventions to maintain focus):

"Using Vyges Conventions, implement the RTL design and testbenches for ASIC/FPGA flows using open-source tools. Include:

  • SystemVerilog RTL following the architecture specification
  • cocotb testbenches with comprehensive test cases
  • Yosys-based synthesis targets
  • Updated vyges-metadata.json with implementation details

Ensure the implementation matches the requirements from Step 2."

This gives you:

  • Synthesizable RTL
  • Structured testbenches
  • CI-ready metadata and build logic

If you need adjustments, re-prompt your AI-IDE with specific requirements (maintain Vyges Conventions focus):

"Using Vyges Conventions, the generated RTL needs these specific changes:

  • [List specific changes needed]
  • [Performance requirements]
  • [Interface modifications]

Please update the implementation accordingly while following Vyges standards."

You can refine this iteratively until the design meets your exact specifications.

✅ Step 4 — Run Local Tests

On Mac (Homebrew) install these open-source tools: (for Ubuntu, use sudo apt install)

brew install verilator icarus-verilog yosys python3

pip install cocotb

Then run tests locally: make lint sim synth

📊 Step 5 — Customize Reporting and CI

Customize Reporting Scripts

The repository template includes generic reporting scripts in the scripts/ directory:

  • Coverage reports for functional verification
  • Synthesis reports for area, timing, and power
  • Linting reports for code quality
  • Test results summaries

Customize these scripts for your IP (AI context automatically loaded):

"Using Vyges Conventions, update the reporting scripts in scripts/ directory to generate reports specific to my [IP_NAME], including [specific metrics or formats needed]."

You can modify these scripts to:

  • Generate custom metrics for your IP
  • Format reports for your team's needs
  • Integrate with external tools
  • Create dashboards for monitoring

Update GitHub Actions for Your IP

The template comes with vanilla GitHub Actions workflows. Customize them for your specific IP:

  1. Update workflow files in .github/workflows/ to match your IP requirements
  2. Modify build targets to include your specific RTL files
  3. Adjust test parameters for your design specifications
  4. Update tool versions if needed for your IP

Your AI-IDE can help customize these workflows (with Vyges context automatically loaded):

"Using Vyges Conventions, update the GitHub Actions workflows in .github/workflows/ to match my [IP_NAME] requirements, including the correct RTL files, test parameters, and synthesis targets."

☁️ Step 6 — Push and Run CI

Push your changes to GitHub. If your repo is public, GitHub Actions will automatically:

  • Lint the RTL
  • Simulate with Icarus or Verilator
  • Synthesize with Yosys
  • Generate customized reports
  • Add status badges to commits and pull requests

Congrats — you now have a reusable, versioned IP block with automated CI/CD and reporting!

📺 Watch It in Action

▶️ Watch the Vyges demo

This 2-minute video walks through:

  • Creating the repo
  • AI-generated design
  • Implementation generation

🔗 Next Steps

Once your IP is ready:

  • Verify the vyges-metadata.json file contains all required information
  • Ensure your RTL follows the {block}_{module}.sv naming convention
  • Run all local tests: make lint, make sim, make synth
  • Customize GitHub Actions workflows for your IP requirements
  • Update reporting scripts to generate IP-specific metrics
  • Push to GitHub and verify CI/CD pipeline success
  • Submit it via vyges.com/contact

We'll onboard it into the Vyges catalog, enabling reuse and visibility across the community.

🌟 Pro Tips for Success

1. Follow Naming Conventions

Vyges uses the {block}_{module}.sv pattern:

  • uart_controller.sv for a UART controller module
  • spi_master.sv for an SPI master module
  • pwm_generator.sv for a PWM generator

2. Leverage AI Prompts

The more specific your prompts, the better the results. Remember: The AI already knows Vyges conventions from the intelligent context files!

Generic prompt (less effective):

"Create a UART controller with 8-bit data width, configurable baud rate, and cocotb testbench following Vyges conventions"

Specific prompt (more effective):

"Create a UART controller with:

  • 8-bit data width with configurable parity (none, even, odd)
  • Configurable baud rates: 9600, 19200, 38400, 57600, 115200
  • 32-deep FIFO buffers for TX and RX
  • Interrupt generation on FIFO threshold, error conditions
  • AXI4-Lite interface for register access
  • Status registers for FIFO levels, error flags, busy status
  • cocotb testbench covering all baud rates, FIFO operations, and error conditions

Follow Vyges naming conventions: {block}_{module}.sv pattern"

3. Use the Template Structure

Don't reinvent the wheel - the template provides:

  • Standard directory layout
  • Pre-configured build targets
  • CI/CD pipeline setup
  • Metadata templates

4. Test Early and Often

Run local tests before pushing:

  • Quick syntax check: make lint
  • Functional verification with waveform generation: make sim VCD=1
  • Synthesis validation: make synth

5. Simulation and Waveform Analysis

Enable VCD Generation: During testbench compilation, ensure simulation is enabled to generate *.vcd files for waveform analysis.

Waveform Viewing Options:

  • Local: Use GTKWave for offline waveform analysis
  • Online: Use Surfer Project for browser-based waveform viewing
  • Cloud: Upload VCD files to cloud-based waveform viewers for team collaboration

Simulation Commands:

  • Generate VCD files during simulation: make sim VCD=1
  • View waveforms with GTKWave: gtkwave waveform.vcd
  • Or use online Surfer for quick waveform checks. Upload your .vcdfile to https://app.surfer-project.org/index.html

🚀 Advanced Workflows

Custom IP Types

Extend the template for specialized IP:

  • Analog/mixed-signal blocks
  • Memory controllers
  • Communication protocols
  • Custom accelerators

Team Collaboration

Use Vyges for team development:

  • Shared naming conventions
  • Automated quality gates
  • Consistent documentation
  • Version control best practices

Integration with Existing Tools

Vyges works alongside:

  • Commercial EDA tools
  • Custom build systems
  • Existing IP libraries
  • CI/CD pipelines

🔧 Troubleshooting Common Issues

Build Failures

  • Check tool versions: verilator --version yosys --version iverilog --version
  • Verify dependencies: pip list | grep cocotb

CI/CD Issues

  • Ensure repository is public for free GitHub Actions
  • Check workflow file syntax
  • Verify tool versions match local environment

RTL Issues

  • Use make lint for syntax checking
  • Verify SystemVerilog compatibility
  • Check port naming conventions

Simulation Issues

  • Ensure VCD generation is enabled: make sim VCD=1
  • Check VCD file creation in simulation output
  • Verify waveform viewer compatibility (GTKWave, Surfer Project)
  • For online viewing, ensure VCD files are properly formatted

🚀 Stay Connected & Follow Along

Questions? Comments? Need help? We want to hear from you!

Join the Vyges Community

Important Note for Developers

A word of caution: Just because you can compile the RTL with tests and run reports does not mean the functionality will work on silicon. RTL simulation and synthesis are essential steps, but they don't guarantee silicon success.

What you've achieved so far:

✅ RTL that compiles and simulates correctly
✅ Testbenches that pass functional verification
✅ Synthesis that completes without errors
✅ Automated CI/CD and reporting

Follow us on upcoming blog posts as we guide you through building your first chip from RTL to silicon!

Follow Our Journey to Silicon

This is just the beginning! In upcoming posts, we'll cover:

  • 🔬 Physical Design Fundamentals - From RTL to GDSII
  • ⏱️ Timing Closure - Clock domains, setup/hold, and STA
  • 🔋 Power Analysis - IR drop, electromigration, and thermal design
  • 🏭 Manufacturing Prep - DRC, LVS, and tapeout considerations
  • 🧪 Post-Silicon Validation - Real-world testing and characterization

🔍 Final Pro Tip: Cross-Check Vyges Conventions

Before submitting your IP, verify that all Vyges Conventions rules are followed:

"Review my entire IP implementation and check if all Vyges Conventions rules are followed, including:

  • File naming: {block}_{module}.sv pattern
  • Directory structure compliance
  • Metadata completeness in vyges-metadata.json
  • Naming consistency across RTL, testbenches, and constraints
  • Interface standardization

Flag any violations and suggest corrections."

This final check ensures your IP meets Vyges standards and will integrate seamlessly with the ecosystem.

About the Author: Shivaram Mysore is the Founder and CEO of Vyges. With over two decades of experience at the intersection of software, standards, open-source and platform infrastructure with startups and companies such as Sun, Microsoft and Infoblox, Shivaram brings a rare cross-disciplinary lens to modernizing silicon development.

📬 Stay Updated

Don't miss our latest insights on silicon IP development and platform updates. Subscribe to our RSS feed for automatic updates:

RSS Icon Subscribe via RSS | 📧 Contact us | 👀 Follow us on X, LinkedIn