VyCatalog: The Home of Free Silicon IP

The first open registry for silicon IP — 125+ machine-readable IPs and growing.

May 1, 2026 • By Shivaram Mysore

The Gap That Silicon Had

PyPI for Python. npm for JavaScript. Crates.io for Rust. Maven Central for Java. Every modern software ecosystem has a place where reusable building blocks are catalogued, version-controlled, and one command away from your project.

Silicon, until now, had no equivalent.

If you needed a UART, an SPI controller, or an FFT block for your next chip, you had three uncomfortable options: a vendor catalog (proprietary, expensive, locked-in), an internal Excel sheet of "things our team has built before" (drift-prone, half-documented), or a deep dive through GitHub repositories hoping the README told you enough to actually integrate. None of these scale.

VyCatalog closes that gap.

What VyCatalog Is

VyCatalog is the first open registry for silicon IP. 125+ open-source silicon IPs at launch, machine-readable, free to use, and growing.

Every IP block in the catalog is described by the Vyges Metadata Standard — a JSON Schema (Draft 2020-12) that captures the entire IP definition: interfaces, registers, parameters, target PDKs, integrity status, and license. The Vyges Metadata Standard turns the spreadsheet into a code artifact — registers, parameters, and interfaces version-controlled with the RTL, not maintained as separate spec docs.

What's In It

The 125+ entries cover the building blocks of modern SoCs:

  • CPU cores — RISC-V (including Ibex)
  • System buses — APB, TileLink Uncached Lightweight (TL-UL), AXI, OBI
  • Peripherals — UART, SPI, I²C, GPIO, interrupt controllers
  • DSP and math — Fast Fourier Transform (FFT), CORDIC
  • Memory — SRAM macros, register files
  • Mixed-signal — analog-to-digital converters (ADC), temperature sensors

…and more. Browse the full catalog — the list grows as new IPs are indexed and verified.

The IP Nutrition Label

Every entry in VyCatalog ships with what we call an IP Nutrition Label — borrowed from FDA food labels for instant comprehension.

You wouldn't open every cereal box at the grocery store and taste it before buying. You read the label.

In silicon, "tasting" means reading the RTL — every interface, every register, every state machine. Engineers need (System)Verilog fluency to evaluate. AI tools burn tokens parsing it from scratch every time. Labels avoid both costs.

The label normalizes across IPs the same way an FDA food label normalizes "salt" vs "sodium bicarbonate" — different underlying source, one readable surface. Bus, registers, timing, integrity status, license, target PDK — all scannable in seconds. Engineers scan it; AI agents consume it directly.

Why It's Open

A proprietary registry would cap supply; an open one compounds it.

The economic logic is straightforward: if Vyges ran the registry as a paid product, supply would be bounded by who pays Vyges. Run it open, and supply is bounded by who shows up — a far larger set. Every IP that lands in the catalog makes the next chip faster.

The public registry is free, and stays free.

For organizations with proprietary, embargoed, or licensed IP that cannot sit in a public catalog, we offer VyCatalog Enterprise — the same registry engine and the same metadata standard, deployed inside your perimeter (on-premise, your cloud, or Vyges-managed). One engine, one metadata model, two configurations. The public catalog scale-tests the enterprise deployment; fixes flow in both directions; there is no fork.

How To Use It Today

  1. Browse — go to vyges.com/products/vycatalog/ and click any IP. The label tells you what you're getting in seconds.
  2. Integrate — clone the repository, drop the RTL into your design, follow the metadata's interface contract.
  3. Contribute — got an open-source silicon IP? Apply the Vyges Metadata Standard and submit it. The standard itself is open.

Today this happens through Git and the catalog's web UI. Coming soon: Vyges CLI — the package manager for silicon IP, same pattern as npm for npmjs.org or pip for PyPI. Vyges CLI is in early access; contact us for access.

What's Next

The next post in this series will show how Vyges itself used VyCatalog to compose a fab-ready SoC in weeks — eight verified blocks from the registry, integrated, verified, hardened, and submitted to fab. We will publish that post once the contest submission goes through.

Closing

Software has PyPI, npm, and Crates.io. Until VyCatalog, silicon had nothing equivalent.

That is changing.

→ Browse VyCatalog → Read the Vyges Metadata Standard → Vyges CLI early access