Research

Publications

Papers from the Vyges team on open silicon sign-off and AI-native chip design.

Systems architecture

Vyges Loom: A Shared Data-Spine Architecture for Open Sign-Off and Physical Design Optimization

An open (Apache 2.0) architecture that brings sign-off-quality timing closure — and the optimization that closes it — to open process nodes, unifying analysis, optimization, and verification over one shared data model.

Shivaram Mysore, Vyges

AI & orchestration

Deterministic Core, Agent Tail: A Verify-Before-Ship Architecture for Orchestrating Open Silicon Sign-Off

A reliability pattern for applying language models to sign-off-grade chip design: a large deterministic core of trusted engines with a thin agent tail, governed by a verify-before-ship gate that never ships a result it cannot confirm.

Shivaram Mysore, Vyges