# Vyges > Vyges is AI-native silicon engineering: bring your AI model, your PDK, and your IP, and turn them into fab-ready silicon in weeks, not months. A model reasons about the design; deterministic engines do the work. Vyges includes an open registry of verified hardware IP (150+ blocks), a suite of open-source EDA sign-off engines (Apache-2.0) that any AI model can drive locally through `vyges mcp`, an end-to-end flow, and a taped-out SoC — so teams design, verify, and tape out chips without six-figure tool licenses. Vyges is the execution layer for AI-native silicon engineering. Any AI model — Claude, OpenAI, Grok, an open-weight model (Qwen, Llama, DeepSeek), or a semiconductor-specific model such as SemiKong — can drive the deterministic engines through the open **Model Context Protocol** (`vyges mcp`), on your own hardware so RTL never leaves the building; or run the engines manually from the CLI and CI. The model is **open core**: the engines and tooling are open and runnable today; the only thing gated is per-foundry **calibration plugins** (NDA), which encode confidential process data. Standard file formats (Liberty, SPEF, SPICE, GDSII/OASIS, structural Verilog/Yosys JSON) in and out, declarative job files instead of Tcl, and CI-native exit codes throughout. AI models are replaceable; the silicon flow isn't. Everything below is canonical; descriptions are written to be honest about scope and bounds. ## EDA sign-off engines (open-core, Apache-2.0) - [EDA Engines overview](https://vyges.com/products/loom/): The Vyges Loom sign-off suite over one cross-engine data spine, plus the geometry kernel beneath them; includes an OpenLane/LibreLane adoption guide (pre-P&R shift-left vs post-layout independent sign-off). - [vyges-opendb](https://vyges.com/products/loom/opendb/): The design database layer over OpenROAD's OpenDB — ECO surgery, DEF I/O, connectivity/wire-length reports and a typed query surface, plus **2.5D/3D chiplet assembly**: read a 3Dblox assembly natively into the database, run seven structural checks, verify that the bumps on two mating faces actually meet and carry the same signals (`check-d2d`), and render the stack as a cross-section. One binary, no Tcl, no Python. - [vyges-char](https://vyges.com/products/loom/char/): Standard-cell characterization — SPICE in → Liberty `.lib` (NLDM/CCS/LVF), parallel-SPICE orchestration. - [vyges-extract](https://vyges.com/products/loom/extract/): RC parasitic extraction — routed layout → SPEF; a calibrated sky130 deck tracks OpenRCX to 0.997 on a routed block. - [vyges-power](https://vyges.com/products/loom/power/): Gate-level power (leakage + internal + switching) and the per-instance activity map em-ir consumes — closes char → power → em-ir. - [vyges-sta-si](https://vyges.com/products/loom/sta-si/): Static timing **with signal integrity** → WNS/TNS and the worst path; the SI/crosstalk + statistical-OCV answer OpenSTA lacks. - [vyges-em-ir](https://vyges.com/products/loom/em-ir/): Power-distribution-network sign-off → IR-drop + electromigration against a budget. - [vyges-thermal](https://vyges.com/products/loom/thermal/): On-chip thermal sign-off → peak temperature + hotspot from a floorplan power map, with electro-thermal (leakage ⇄ temperature) coupling; the thermal dual of em-ir. - [vyges-lvs](https://vyges.com/products/loom/lvs/): Layout-vs-schematic — name-independent graph match → MATCH/MISMATCH with the divergence named; native GDS/OASIS extraction; correlated exact vs Magic. - [vyges-drc](https://vyges.com/products/loom/drc/): Geometric design-rule check — GDS or OASIS vs a rule deck (width/spacing/area/density/antenna/enclosure) plus a metal-fill generator; the geometric sibling of LVS. - [vyges-cdc](https://vyges.com/products/loom/cdc/): Clock-domain-crossing check — flags unsynchronized crossings from netlist + Liberty + SDC; the metastability bug a lockstep simulator can't see. - [vyges-glitch](https://vyges.com/products/loom/glitch/): Static glitch/hazard analysis — reconvergent-fanout static + dynamic hazards from the same timing data sta-si uses; the blind spot of cycle-based simulation. - [vyges-lec](https://vyges.com/products/loom/lec/): Combinational logic equivalence — proves two netlists compute the same function across all inputs, with a counter-example on mismatch; the formal complement to simulation. - [vyges-gds-view](https://vyges.com/products/loom/gds-view/): Headless GDS/OASIS layout viewer — GDS or OASIS → layered SVG with an optional violation overlay; the *where* to DRC/LVS's *what*, no GUI. - [vyges-meas](https://vyges.com/products/loom/meas/): Closed analog measurement kernels — coherent single-tone SNR/SINAD/THD/SFDR from a capture, and gain/bandwidth/unity-gain-frequency/phase-margin from an AC sweep. One documented method per metric; a capture it cannot measure that way (non-coherent, clipped, aliased harmonic) is refused rather than approximated, and nothing is extrapolated past the swept range. Vyges definitions, explicitly not a claim of IEEE 1241/1658/1057 conformance. - [vyges-ant](https://vyges.com/products/loom/ant/): Antenna sign-off on the routed design database — the process damage that passes every simulation and shows up as yield loss. Checks PAR/CAR/PSR/CSR at the last stage a protection diode can still fix a violation, and names the gate and the layer rather than only the net, so the fix has somewhere to go. Reads both LEF limit forms (plain ratios and diffusion-dependent PWL curves), so it cannot report clean on a technology whose limits it never read — sky130 states only the curve form. Cross-checked against OpenROAD check_antennas; a fast screen and second opinion in CI, not a replacement for sign-off. ## Design optimization engines (open-core, Apache-2.0) Netlist in, better netlist out — every move scored by the same sta-si timer that gates sign-off. The analysis engines say what is wrong; these fix it. - [vyges-resize](https://vyges.com/products/loom/resize/): Gate sizing — drive-strength resize to close setup or recover area, pre-place or post-place ECO with SPEF. - [vyges-vt-swap](https://vyges.com/products/loom/vt-swap/): Threshold-voltage swap at identical footprint — cut leakage or close setup without moving a cell. - [vyges-buffer-insert](https://vyges.com/products/loom/buffer-insert/): Buffer insertion — splits high-fanout or over-transition nets so the driver's transition returns under limit with timing still met. - [vyges-hold-fix](https://vyges.com/products/loom/hold-fix/): Post-route hold ECO — inserts series delay on hold-violating capture pins, scored against real routed parasitics. - [vyges-remap](https://vyges.com/products/loom/remap/): Multi-output technology re-mapping — recovers the cells a one-output-at-a-time mapper duplicates, worth most on datapath. Every re-map is combinationally equivalence-checked and the area delta is measured against a single-output baseline. Drives external logic tools (mockturtle emap, Yosys, ABC), which are not bundled. ## Products & platform - [Vyges CLI](https://vyges.com/products/vyges-cli/): The command-line front door to the toolchain — find & fetch verified silicon IP from the catalog, present & resolve PDK collateral, and `vyges install loom` to add the open sign-off & optimization engines. Free, single Rust binary, `--json` on every command (terminal, CI, and AI agents). - [Vyges MCP](https://vyges.com/products/mcp/): The local Model Context Protocol server (`vyges mcp`, ships in the CLI) that lets any tool-calling AI model run the engines on your own machine. Exposes the Loom engines *and* the open tools beside them (OpenROAD, Yosys, Magic, Netgen, KLayout, Verilator) through one interface; engines self-describe via `--describe`, so there is no fine-tuning and no prompt library to maintain. Tools are classified read vs design-mutating from their own descriptions, and the `core`/`pro`/`full` profile gate decides which are exposed (default `full`; `VYGES_MCP_PROFILE=core` gives an analysis-only agent). stdio JSON-RPC — no port, no auth, and no Vyges service in the path. - [VyBox](https://vyges.com/products/vybox/): Self-contained EDA environments — a free Cloud-IDE (Lite), an open RTL→GDSII container (EDA), and **VyBox-Sley**, the end-to-end sign-off flow orchestrator (early access). - [VyCatalog](https://vyges.com/products/vycatalog/): An open registry to discover and explore verified hardware IP blocks from the Vyges community. - [VyContext](https://vyges.com/products/vycontext/): The entry point for IP development — operationalize silicon-development methodology inside AI coding tools and IDEs for consistent, compliant, reusable IP. - [VySeal](https://vyges.com/products/vyseal/): Trusted IP signing, encryption, and licensing (IEEE P1735) for delivering IP beyond the EDA walled gardens. - [VyShuttle](https://vyges.com/products/vyshuttle/): Commission-based MPW shuttle service — from verified IP to silicon, integrated with VyBox. - [Post-silicon](https://vyges.com/products/post-silicon/): Development boards and evaluation kits — from silicon to system. - [Free Tools](https://vyges.com/tools/): Free, browser-based tools for silicon IP and chip design — IP compliance checker, interactive chip-layout viewer, IP search, and spec explorers. No login, no license. ## Silicon & technology - [Silicon](https://vyges.com/silicon/): Vyges silicon work, including the taped-out Edge Sensor SoC (sky130A). - [Technology](https://vyges.com/technology/): Why Vyges delivers silicon in weeks, not months — a model-agnostic AI execution layer (bring any model, run locally via `vyges mcp`), the metadata standard, Loom engines, and the MCP interface. AI proposes; Loom verifies. - [Metadata specification](https://vyges.com/technology/metadata-spec/): A standardized, validated format for describing reusable silicon IP blocks. - [PDK specification](https://vyges.com/technology/pdk-spec/): A neutral PDK descriptor schema — one presentation contract over heterogeneous PDKs, 180 nm → 2 nm. - [Design chips, not orchestrate tools](https://vyges.com/technology/tool-sprawl/): Why AI-native silicon engineering — EDA has become a tool-management problem; teams are hired for tool expertise (a PrimeTime engineer, a Calibre engineer, an Innovus engineer), not chip design. AI is collapsing that tax: one interface any AI model drives via `vyges mcp`, so engineers work on the chip, not a dozen tool dialects. - [AI that actually fixes designs](https://vyges.com/technology/ai-fixes/): The failure-to-fix loop — a model reads the verdict, proposes a change, a deterministic Loom optimizer applies it (resize, vt-swap, buffer-insert, hold-fix, DRC repair), and it's re-scored until green. `loom.feedback` gives the agent its eyes; every move is scored by the same sign-off that gates tape-out. AI proposes; deterministic engines fix. - [Context, Capability, Correctness: Three Bets on Trusting an AI Agent](https://vyges.com/about/blog/posts/2026-08-12-context-capability-correctness/): Cloudflare OS bets an agent needs constraining, Spotify Xirp bets it needs context, and neither claims to check whether the agent output is correct; that third question remains largely unsolved. Why correctness is only checkable where the domain supplies an oracle, why silicon is one of those domains, and an honest account of how early that work still is. - [Vyges: First Year Anniversary](https://vyges.com/about/blog/posts/2026-08-11-vyges-first-year-anniversary/): One year from launch — what a year of building silicon like software produced: an open catalog of 160+ IP blocks, the open Vyges Loom sign-off suite, open metadata and PDK standards, and the Edge Sensor SoC taken from specification to tapeout. Also OpenDB brought into Loom as the foundation for chiplet and 2.5D/3D flows, and what year two is for. - [Open-Source EDA Now Has a Chiplet Workflow](https://vyges.com/about/blog/posts/2026-08-11-open-eda-now-has-a-chiplet-workflow/): Advanced packaging was the part of silicon design open tools could not reach. You can now describe a chiplet assembly, check that it is structurally sound, check that its die-to-die interfaces actually connect, draw it, and gate CI on all of it — with open tools, on your own machine. What exists, what it catches, and what is still missing. - [An Open Chiplet Flow, End to End, on OpenROAD](https://vyges.com/about/blog/posts/2026-08-08-an-open-chiplet-flow-on-openroad/): The complete open chiplet workflow — 3Dblox assembly into OpenDB, structural and die-to-die verdicts over one model, a drawing, and a CI gate — plus the five-minute demo where a one-character change kills an 8-bit die-to-die bus and the structural checks stay green. Argues that one semantic model with many deterministic analyses is the right abstraction for open advanced packaging. - [Your Chiplet Interface Passes Every Open-Source Check. It's Still Dead.](https://vyges.com/about/blog/posts/2026-08-05-the-chiplet-check-nobody-is-running/): Two dies are only connected if the bumps on their mating faces land on each other and carry the same signals. A one-character mistake left an entire 8-bit die-to-die bus connected to nothing while every open-source structural check reported zero violations. Measured, with the failure table — and `check-d2d`, the check that catches it. - [Describing and Checking a Chiplet Stack, With Open Tools](https://vyges.com/about/blog/posts/2026-08-02-describing-and-checking-a-chiplet-stack/): An assembly is not a design file — it describes how several dies are placed, flipped and bonded. How to write one in 3Dblox, read it natively into OpenDB, check it, and draw it as a cross-section. Includes the measurement that stopped us shipping a wrong answer: `MZ` does not mirror in X. - [We didn't train the AI — we taught our tools to explain themselves](https://vyges.com/about/blog/posts/2026-07-16-we-taught-our-tools-to-explain-themselves/): No fine-tuning and no orchestration code — every Vyges Loom sign-off engine exposes a typed, self-describing interface, and an off-the-shelf GPT-4.1 model connected through `vyges mcp` discovers the engines and drives the sign-off flow on its own. Orchestration becomes a property of the interfaces, not the model, so today's model isn't special and tomorrow's works too. Watch it run live in a clean cloud runner on the Vyges Loom Testbench dashboard. - [How do I use a local SemiKong LLM to drive DRC sign-off?](https://vyges.com/about/blog/posts/2026-07-09-running-semikong-local-drc/): A hands-on walkthrough — register a local SemiKong with `vyges model`, expose the Loom engines via `vyges mcp`, and drive real `vyges-drc` on a taped-out IP, end to end on your own hardware. Real captured output; the deterministic engine is the ground truth, nothing leaves your machine. - [Point Your AI IDE at Your Own Silicon Tools — Locally, No Cloud](https://vyges.com/about/blog/posts/2026-07-06-point-your-ai-ide-at-your-silicon-tools/): Install the Loom engines, run `vyges mcp setup`, and Claude Code, Cursor or VS Code can drive real DRC, LVS and timing sign-off on your own machine. No cloud, no upload, no auth — the model proposes and the deterministic engine decides. - [Timing Sign-Off for the Open Silicon Era — and Why We Wrote It in Rust](https://vyges.com/about/blog/posts/2026-06-25-commercial-grade-timing-signoff-in-rust/): Open EDA had timing *analysis*, not timing *sign-off*. `vyges-sta-si` is WNS/TNS with signal integrity over foundry-standard formats, CI-native and exiting non-zero on a violation — written in Rust so it runs natively from a MacBook to an Arm64 cloud, parallel by design. - [VyCatalog: The Home of Free Silicon IP](https://vyges.com/about/blog/posts/2026-05-01-vycatalog-open-registry-for-silicon-ip/): Software has PyPI, npm and crates.io; silicon had nothing equivalent. VyCatalog is an open, machine-readable registry of 125+ free silicon IPs, searchable from the CLI with `vyges catalog`. - [VyBox Lite: Cloud-Native Silicon IP Development with GitHub Codespaces](https://vyges.com/about/blog/posts/2025-08-18-vybox-lite-codespaces/): A browser-accessible development environment for silicon IP — pre-configured open EDA tools plus AI assistance, with nothing to install locally. ## Company & docs - [Documentation](https://vyges.com/docs/): Guides for IP development, verification, design types, and tooling. - [About](https://vyges.com/about/): Who Vyges is and why AI-native silicon engineering — silicon is the product; AI and the open toolchain are how we ship it faster. - [Blog](https://vyges.com/about/blog/): Announcements and deep dives. - [Publications](https://vyges.com/about/publications/): Research papers from the Vyges team on open silicon sign-off and AI-native chip design — the Vyges Loom shared-data-spine architecture, and the "deterministic core, agent tail" verify-before-ship pattern for orchestrating sign-off with LLMs. - [Events](https://vyges.com/about/events/): Where to find Vyges — a DAC 2026 Open-Source EDA Birds of a Feather lightning talk, "Using a Semiconductor LLM to Drive Real DRC Sign-Off" (session AM110), and the ICLAD Hackathon 2026 (Vyges, Team 22, cloud and on-site). - [Contact](https://vyges.com/contact/): Talk to the Vyges team — schedule a call, request a demo, partnership, media, or early access, via the contact form.