Silicon

Silicon is not a category we serve — we are a silicon company.

Most silicon programs spend millions and 6–9 months outsourcing integration just to reach tapeout. Vyges replaces that step with fab-ready SoC IP (System-on-Chip IP) — integrated, verified, and deliverable in weeks.

Talk to us about silicon

The wedge — fab-ready SoC IP

Vyges sells fab-ready SoC IP — complete, integrated, and proven — so companies don't have to spend millions and 6–9 months outsourcing integration just to get to tapeout.

Legacy: Outsourced Integration Vyges: Fab-Ready SoC IP
Inputs Buy multiple commercial IPs; mix open + proprietary blocks Select a fully built SoC IP from VyCatalog, or commission one from known reusable blocks
Process Contract an external integration house, long SOW negotiation, manual RTL integration, bespoke verification, ad-hoc docs, hand-offs between teams Pre-integrated, verified, metadata-complete SoC; hardened macros; known PDK targets; CI-verified build → sign → package → synthesize
Time 6–9 months minimum Weeks
Cost $2–5M+ before first silicon Order-of-magnitude reduction
Fab ownership Integration vendor owns it Vyges can take it to the fab; deliverables are fab-ready on day one
Reuse next time Limited — bespoke output Versioned, registered, composable for the next program

Vyges sells productized silicon artifacts, not labor or scoped design services.

Fab-ready integration delivered in weeks — not units licensed or engineer-hours billed. Engagement scoped to your requirements.

What "weeks" means

Typical engagements deliver a fab-ready, signoff-clean GDS for a known PDK in weeks, not months.

What "product, not bespoke" means

Fab-ready SoC IPs are versioned artifacts built from registered blocks — new programs compose and extend, rather than restart integration.

How We Ship Silicon in Weeks

Push on Green Silicon

Vyges operates a fully automated silicon delivery pipeline where a change that passes all verification gates can be promoted to a fab-ready artifact with no human handoffs. This yields speed, repeatability, and auditability across every chip we ship.

If it's green, it's shippable.

This discipline is enforced by internal generation and CI systems used exclusively to deliver Vyges silicon products.

What we've shipped

Status legend: shipped = public & in use · submitted = entered into a public process · verified = end-to-end pipeline run on a real artifact · hardened = through OpenLane to GDS · taped out = sent to fab

Artifact Status Evidence
VyCatalog™ — open silicon-IP registry shipped 125+ IPs Browse VyCatalog
Edge Sensor SoC submitted Chipfoundry Contest 2026 GitHub · contest link pending
VySeal™ pipeline verified 2026-04-02 End-to-end run
OpenLane macro library hardened 7 macros, incl. SRAM Macro list

The Edge Sensor SoC — Chipfoundry Contest submission

submitted

What it is

The Edge Sensor SoC is a fully integrated, fab-targeted system-on-chip submitted to the Chipfoundry Contest. It demonstrates Vyges' ability to deliver fab-ready SoC IP — pre-integrated, verified, and metadata-complete — without the months-long outsourced integration typically required to reach tapeout. The contest entry also includes firmware, a reference PCBA, and a mechanical enclosure — showing the SoC working end-to-end in a complete edge-sensing system, not as a bare die on a tester.

  • CPU: Ibex (RISC-V)
  • Peripherals: UART, SPI, FFT accelerator, PLIC
  • Target PDK: Sky130
  • Integration: End-to-end via Vyges registry, generators, and CI
  • System deliverables: firmware (runs on the SoC), reference PCBA (hosts the chip), and mechanical enclosure (productized form factor) — produced alongside the SoC for the contest entry
  • Status: Submitted to Chipfoundry Contest (2026)
Edge Sensor SoC block diagram — Ibex + UART + SPI + FFT + PLIC

Block diagram

Edge Sensor SoC user_project_wrapper floorplan

Hardened floorplan (user_project_wrapper)

Mechanical enclosure render of the Edge Sensor SoC complete system

Mechanical enclosure (productized form factor)

The firmware, PCBA, and mechanical enclosure exist to demonstrate the SoC in a real edge-sensing application — they are proof that the chip works at the system level, not a separate Vyges product line. Note: this submission does not involve VySeal — VySeal is a separate, independently verified artifact (see "What We Ship").

FPGA Hardware Validation

FPGA is evidence of correctness, not the product. It exists to prove the SoC integration works before tapeout.

As part of pre-silicon validation, the Edge Sensor SoC has been synthesized and validated on FPGA hardware. This FPGA bring-up exercises the same integrated SoC design submitted for silicon, providing early functional confidence prior to tapeout.

  • • End-to-end SoC build validated on FPGA hardware
  • • CPU, peripherals, and interconnect exercised on real hardware (not simulation-only)
  • • Same RTL used for the Chipfoundry Contest submission
  • • Reference: FPGA Hardware Validation
Edge Sensor SoC FPGA bring-up animation

Edge Sensor SoC FPGA bring-up (pre-silicon validation)

Contest submission status

VySeal™ end-to-end pipeline

verified 2026-04-02

VySeal is the IP licensing and delivery infrastructure for commercial silicon. The end-to-end pipeline — sign → package → deliver → synthesize — was verified end-to-end on 2026-04-02 against a real Vyges commercial IP block, producing a synthesizable result downstream of the delivered package.

Stage 1
Sign
Author signs the IP package
↓
Stage 2
Package
Sealed bundle assembled
↓
Stage 3
Deliver
Recipient verifies and unlocks
↓
Stage 4
Synthesize
Synthesizable result downstream

VySeal end-to-end pipeline — verified 2026-04-02

OpenLane macro library

hardened

Seven hardened GDS macros — the building blocks underneath the Edge Sensor SoC — taken through OpenLane to GDS on Sky130, including SRAM macros.

rv_core_ibex_tlul
Ibex CPU core, TL-UL bus
xbar_main
Main TL-UL crossbar
fft_ctrl_tlul
FFT accelerator (incl. SRAM)
spi_host_lite
SPI host controller
uart
UART peripheral
rv_plic_lite
RISC-V interrupt controller
edge_sensor_glue
Top-level integration glue
OpenLane macro library — all 7 hardened macros placed in user_project_wrapper

All 7 hardened macros placed in the user_project_wrapper, Sky130

GDS files: vyges-edge-sensor-soc/gds/.

Vyges builds silicon products; the registry and infrastructure are how we compound speed, reuse, and trust across generations of chips.

License fab-ready SoC IP, or commission silicon?

Vyges builds and licenses fab-ready SoC IP and commissions silicon for buyers who would otherwise spend millions and months on outsourced integration.

Talk to us about silicon Browse VyCatalog