Events
Where the Vyges team is showing up next — and recordings and write-ups from where we have already been.
ORConf 2026 · Talk
Sept 11–13, 2026 · Zebrastraat, Ghent, Belgium
Shivaram Mysore presents at ORConf 2026, the FOSSi Foundation’s open silicon conference. Reusing an IP block means trusting someone else’s claims about it. The talk covers the two halves of making those claims checkable: Vyges VyCatalog™, an open machine-readable registry for silicon IP with validated metadata for RTL interfaces and PDK targets, and Vyges Loom™, an open sign-off suite — geometric DRC, LVS, RC extraction, and static timing with signal integrity — that lets you verify the claims yourself instead of taking them on faith.
We are usually at DAC and the open-silicon conferences, and we are happy to talk to a team that is evaluating open EDA.
Get in touch →DAC 2026 · Panel
Tue, July 28 · 8:30–9:10 PM · Room 104C
Shivaram Mysore joined the Open-Source EDA Birds of a Feather panel as the industry voice, alongside panelists from Arizona State, Brown, Columbia, ETH Zurich and Silimate. The question on the table: if AI can build what you describe, what should engineers be learning instead? Our answer — AI makes generating a design cheap, and makes proving it correct the skill that matters.
DAC 2026 · Birds of a Feather
Tue, July 28 · 9:10–9:30 PM · Room 104C
A lightning talk by Shivaram Mysore in the Open-Source EDA Birds of a Feather session (AM110) at the 63rd Design Automation Conference (DAC), 2026 — a live run showing an LLM driving real DRC sign-off, with the checking left to deterministic tools.
2026 · Hackathon
July 2026
Vyges competed in the ICLAD Hackathon as Team 22, entering both the cloud and on-site tracks.