Vyges™ Loom

RTL in, a mapped netlist out — synthesis inside the suite, so a flow runs from RTL to layout without leaving it.

What it does

Elaborates SystemVerilog, synthesizes it on the shared AIG core, and maps it onto the Liberty library's cells, writing a structural Verilog netlist. A timing-driven resynthesis pass reworks the logic around each failing gate output after placement, from Ashenhurst–Curtis decompositions.

In → out

.sv RTL + .lib  ──►  vyges-syn  ──►  mapped netlist (.v)

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical syn

License

Apache-2.0

Used by: anyone taking RTL to gates who wants synthesis on the same core as restructuring and formal.

Multi-output technology re-mapping — recovers the area a one-output-at-a-time mapper leaves behind, and proves the function did not change before it hands the netlist on.

What it does

A conventional technology mapper covers one output at a time, so a cell that could have driven several outputs gets duplicated once per output. In arithmetic and datapath logic, where sub-expressions are shared everywhere, that duplication is a standing area tax. vyges-remap re-maps the same logic with a multi-output covering, then reports the before/after cell and area delta against a single-output baseline it computes itself — so the gain is measured, not asserted.

In → out

mapped netlist  ──►  vyges-remap  ──►  smaller netlist + measured delta, equivalence-checked

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom remap

License

Apache-2.0

Used by: anyone whose block is over its area budget after synthesis — particularly datapath, where the shared structure is the whole point.

Restructure the logic, not just the cells — re-synthesis of timing-critical or area-heavy regions, with every rewrite checkable for equivalence.

What it does

Pulls the logic behind every failing end point (or an area-heavy region) out of the design, re-synthesizes it on an AIG, and puts the result back. Searches over rewrite sequences — annealing or genetic — find the best worst slack. Built on the same AIG and SAT core as the formal engine, so every rewrite can be proved equivalent.

In → out

.odb + .lib + .sdc  ──►  vyges-rmp  ──►  restructured .odb

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical rmp

License

Apache-2.0

Used by: anyone closing timing or recovering area after placement, where resizing alone is not enough.

Logic equivalence check — did that synthesis, ECO or hand-edit keep the logic the same? Prove two netlists compute the same function across all inputs — or get the one input where they differ.

What it does

Every synthesis, ECO and hand-edit is a promise that the logic still means the same thing. Simulation can only spot-check that promise on the vectors you happened to run. vyges-lec proves it across all 2ⁿ inputs at once — or hands you the one input where the promise broke. It is the formal complement to simulation: it builds a canonical decision diagram for every output of both designs, so equal functions are provably equal, and a mismatch yields a concrete counter-example.

In → out

golden.v + revised.v + .lib  ──►  vyges-lec  ──►  EQUIVALENT ✓ / NOT ✗ (+ counter-example)

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical lec

License

Apache-2.0

Used by: anyone who edits a netlist after synthesis — an ECO, a clock-gate insertion, a hand-fix — and needs to know the logic still means the same thing.

Turn a die rectangle into a floorplan a tool can place into.

What it does

A floorplan is not a rectangle. It is a core area snapped to a site grid, tiled with rows of a definite height, orientation and phase — and every placer, every tap inserter and every power grid after it is built on those rows. Get the grid wrong and nothing downstream is legal.

In → out

.odb + die/core rectangles + site  ──►  vyges-ifp  ──►  rows, core area, instance census

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical ifp

License

Apache-2.0

Used by: anyone starting a block — this is the first thing that runs, and everything downstream inherits whatever it decides.

Power intent for multi-supply designs — which logic sits in which domain, and what guards each crossing.

What it does

Reads a UPF file into the design database — power domains, logic ports, power switches, isolation and level-shifter strategies — and writes the database's intent back out as UPF. It then evaluates the intent, inserting the isolation and level-shifter cells it calls for. A UPF construct it cannot read exactly is refused, never guessed at.

In → out

.odb + .upf  ──►  vyges-upf  ──►  .odb with power domains · .upf

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical upf

License

Apache-2.0

Used by: anyone with more than one supply: analog and mixed-signal chips, and digital blocks with switched or retention domains.

Lay the IO ring around the die, and place what sits in it.

What it does

The IO ring is the band of rows around the die that pads, corners and bumps are placed into. Its geometry is unforgiving: the ring is the die inset by an offset, its corners sized from the corner site, and its four edges truncated to whole sites — a remainder that does not fill a site is given up rather than rounded out.

In → out

.odb + site names + offset  ──►  vyges-pad  ──►  IO rows (name, site, origin, orientation, pitch), placed pads and corners

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical pad

License

Apache-2.0

Used by: anyone taking a block to a package — the ring is the boundary between your design and the outside world.

Put the IO pins where they cost the least wire.

What it does

Every pin on a block boundary is a decision that the router then has to live with. Placed badly, pins add wire to every net that reaches them — and unlike most placement problems, this one has a clean optimum within a section.

In → out

.odb + layer choice + constraints  ──►  vyges-ppl  ──►  pin positions, total wirelength, unplaced pins named

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical ppl

License

Apache-2.0

Used by: anyone placing pins on a block boundary, where a bad assignment costs wirelength on every net that crosses it.

Put the macros where the block can be built around them.

What it does

Macros are the immovable furniture of a block. Once they are down, they define the channels the standard cells live in, the paths the power straps take, and the wire length every net after them has to pay. Put them badly and no amount of downstream effort recovers it.

In → out

.odb + macro coordinates or a netlist to cluster  ──►  vyges-mpl  ──►  macro locations, orientations, placement blockages

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical mpl

License

Apache-2.0

Used by: anyone hardening a block with SRAMs, register files or hard IP — where the macros sit decides the shape of everything placed after them.

Cut the rows around macros, and place the physical cells that keep them legal.

What it does

Rows cannot run through a placed macro, and a row that simply stops needs its ends capped. Meanwhile the wells under the standard cells have to be tied to supply at a spacing the process dictates. Both are invisible in simulation and both are silicon failures when wrong.

In → out

.odb with macros  ──►  vyges-tap  ──►  cut rows + taps + endcaps (master, position, orientation)

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical tap

License

Apache-2.0

Used by: anyone with a macro in their floorplan, or a process that requires well taps at a maximum spacing.

Build the power grid — and refuse the one the technology cannot hold.

What it does

The power distribution network is the structure everything else sits inside. It is built from a small vocabulary — rings around the core, straps across it, follow pins along the standard-cell rows — and then vias connect the layers wherever those shapes cross.

In → out

.odb + grid spec (rings, straps, follow pins)  ──►  vyges-pdn  ──►  grid shapes, vias, block terminals

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical pdn

License

Apache-2.0

Used by: anyone who needs power to reach the cells — and anyone who has debugged a grid that looked fine until the via stage.

Find the open strap where the grid is built — connectivity and static IR drop on the design database, before extraction.

What it does

Reads the power grid straight from the design database and answers two questions: is every instance actually connected to the supply, and how much voltage does it lose on the way (static IR drop, per node, with optional electromigration). It can also export the grid as a SPICE deck for an independent solve.

In → out

.odb (+ voltage file)  ──►  vyges-psm  ──►  connectivity verdict · IR drop · SPICE

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical psm

License

Apache-2.0

Used by: anyone building a power grid who wants a starved macro or a disconnected strap caught at floorplan, not at sign-off.

Spread the standard cells across the core — the first placement every later stage refines.

What it does

After the floorplan and the macros, the standard cells need somewhere to go. Global placement finds a position for every one of them that keeps connected cells close — the starting point legalization, clock-tree synthesis and routing all build on.

In → out

.odb + JSON job  ──►  vyges-gpl  ──►  placed design (DEF) + per-round report

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical gpl

License

Apache-2.0

Used by: anyone taking a netlist to layout — global placement decides where every cell starts, and every later stage inherits it.

Repair the placed design before you trust its timing.

What it does

A freshly placed design breaks electrical rules everywhere: wires too long for their driver, nets loaded past their capacitance limit, transitions slower than the library allows. Until those are fixed, a timing report is measuring a circuit that will not behave as modelled.

In → out

.odb + Liberty + SDC + JSON job  ──►  vyges-rsz  ──►  repaired design (DEF) + decision trace

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical rsz

License

Apache-2.0

Used by: anyone closing a placed block — slew, capacitance and wire-length violations have to be gone before timing means anything.

Seat every cell on a legal site — then prove it.

What it does

Global placement puts cells close to where they should be, not where they can be. Detailed placement moves each one onto a legal site — on a row, aligned to the site grid, overlapping nothing — while moving it as little as possible.

In → out

.odb  ──►  vyges-dpl  ──►  legalized .odb + placement check (per rule family)

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical dpl

License

Apache-2.0

Used by: anyone between global placement and routing — an illegal placement turns into a routing failure or a DRC error later, and much harder to trace.

A chip has to be testable once it is made — scan replacement and chain stitching on the placed design.

What it does

Replaces each flip-flop with its scan equivalent from the library and stitches them into scan chains, so a tester can set and read every register. The chain plan — how many chains, how long, in what order — is reported before it is executed, so you see what will change before it does.

In → out

.odb + .lib + .sdc  ──►  vyges-dft  ──►  scan-stitched .odb + chain plan

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical dft

License

Apache-2.0

Used by: anyone taking a design to production silicon, where every part has to pass a tester.

Find every clock, choose its buffers, and collect every sink it has to reach.

What it does

Before a clock tree can be built, the tool has to know what it is building with and what it has to reach. Which buffers may drive a clock? Which nets are clocks at all, once they pass through clock gates and bidirectional pads? Which flip-flops sit at the end of each one?

In → out

.odb + Liberty + SDC + JSON job  ──►  vyges-cts  ──►  clock nets, sinks and buffer choices (JSON)

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical cts

License

Apache-2.0

Used by: anyone with a clocked design — which is every design; the clock network is where skew, power and hold all begin.

The shape of every net, before it is routed.

What it does

Before a net is routed, its wiring is a guess — and the quality of that guess decides how good every estimate built on it can be. The standard guess is a rectilinear Steiner minimal tree: the shortest set of horizontal and vertical wires that connects all of a net's pins.

In → out

pin coordinates + driver (JSON)  ──►  vyges-stt  ──►  Steiner tree (branches, Steiner points, wirelength)

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom stt

License

Apache-2.0

Used by: every engine that needs to know how a net will be wired before it is — estimation, repair and global routing all start here.

Every net's RC, from placement — without waiting for the router.

What it does

Timing a placed design needs the resistance and capacitance of wires that do not exist yet. Parasitic estimation fills that gap: it predicts each net's wiring and turns the prediction into an RC network the timer can use.

In → out

.odb / LEF + DEF + Liberty + JSON job  ──►  vyges-est  ──►  .spef per corner

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom est

License

Apache-2.0

Used by: anyone timing a placed design — placement-stage timing is only as good as its parasitic estimate.

Plan every net's route across the die — the guides detailed routing works within.

What it does

Routing a whole design wire by wire, all at once, is intractable. Global routing breaks it up: it divides the die into a coarse grid, decides which grid cells and layers each net will pass through, and resolves congestion before a single real wire is drawn.

In → out

.odb / LEF + DEF + JSON job  ──►  vyges-grt  ──►  route guides + .odb + SPEF

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical grt

License

Apache-2.0

Used by: anyone routing a block — global routing decides where congestion lands and which nets get the short way through.

Turn route guides into real wires and vias — until no design-rule marker stands.

What it does

Global routing says which region each net passes through. Detailed routing draws the actual wires and vias, on tracks, obeying every spacing, width and via rule the technology defines — and keeps repairing until the design is clean.

In → out

.odb with route guides  ──►  vyges-drt  ──►  routed DEF or .odb + JSON report

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical drt

License

Apache-2.0

Used by: anyone taking a block to GDS — detailed routing is where the design becomes manufacturable metal.

Find antenna violations before they become silicon failures.

What it does

During fabrication, a long run of metal connected to a transistor gate acts as an antenna: it collects charge from the plasma etch and dumps it through the thin gate oxide. Too much metal per unit of gate area and the oxide is damaged — a device that passes every simulation and fails in silicon. The foundry states the limit as a set of ratios in the LEF, and the layout has to stay under them.

In → out

routed .odb  ──►  vyges-ant  ──►  antenna violations (gate · layer · value vs limit), CI exit code

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom ant

License

Apache-2.0

Used by: anyone taking a routed block to a foundry — antenna damage passes every simulation, survives every functional test, and turns up as yield loss.

Fill the gaps until every layer meets its density floor.

What it does

Foundries require each metal layer to carry a minimum density across the die, because chemical-mechanical polishing behaves badly over large empty regions. Meeting that floor means placing fill shapes into every gap the design leaves — without touching a real wire, a real instance or a real obstruction.

In → out

.odb + JSON fill rules  ──►  vyges-fin  ──►  fill shapes (layer, mask, OPC flag, coordinates)

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical fin

License

Apache-2.0

Used by: anyone streaming out to a foundry — density rules are a tape-out gate, and fill is how you pass them.

Interconnect parasitic extraction — turn a layout's RC into SPEF, from one declarative job, so timing and power see the real wires. Analog and mixed-signal layouts too — RC is geometry, not cell-specific.

What it does

vyges-extract reads a layout and the PDK's parasitic rules and produces SPEF — the resistance and capacitance of every net. That's what lets static timing and power analysis reason about the actual interconnect, not an idealized one. SPEF is the standard hand-off the downstream engines expect. Extraction accuracy is governed by the PDK's parasitic rules — the engine is open, the calibration is foundry-specific; it handles hierarchical, full-chip designs.

In → out

layout (DEF/LEF) + parasitic rules  ──►  vyges-extract  ──►  .spef (RC parasitics)

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom extract

License

Apache-2.0

Used by: physical-design flows that want timing and power to see real wires — not estimates.

Static timing analysis with signal integrity — WNS / TNS and the worst path, from one declarative job, with a CI gate that fails on a violation.

What it does

vyges-sta-si checks whether the design meets timing — reporting worst negative slack (WNS), total negative slack (TNS), and the critical path — while accounting for signal-integrity coupling between nets (crosstalk-induced delay and noise effects). It reads the .lib from vyges-char and the .spef from vyges-extract — the two upstream artifacts on the spine. The timing results and slack metrics are sign-off compatible with standard Liberty and SPEF inputs — no proprietary formats, no hidden transforms.

In → out

.lib + .spef + design & constraints  ──►  vyges-sta-si  ──►  WNS / TNS / worst path

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom sta-si

License

Apache-2.0

Used by: platform and PD teams gating timing on every commit — sign-off as a check, not a late-stage review.

Power analysis — leakage + internal + switching from a netlist and activity, against a budget. Emits the per-instance activity that em-ir needs.

What it does

vyges-power reads a gate-level netlist and the Liberty models and computes power — leakage, internal, and switching — from either a vectored activity file (VCD) or vectorless probabilistic toggling. Just as importantly, it emits the per-instance activity / current map that vyges-em-ir consumes, so IR-drop is solved from real per-instance current instead of a worst-case assumption — closing the char → power → em-ir loop.

In → out

netlist + .lib + activity (VCD / vectorless)  ──►  vyges-power  ──►  power report + activity map → em-ir

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom power

License

Apache-2.0

Used by: teams who need a power number early — and the activity map that makes IR-drop analysis real.

Power-integrity sign-off — solve the power-distribution network for IR-drop and electromigration against a budget, from one declarative job. Digital, analog and mixed-signal power grids alike — it's grid physics, not a standard-cell construct.

What it does

vyges-em-ir takes the design's power-distribution network (PDN) and solves it — reporting IR-drop (how much supply voltage the grid loses) and checking electromigration (EM) current limits against a budget. The per-switch energy seam from vyges-char feeds its dynamic solve, so power integrity is consistent with the cells' characterized behavior. It reports both steady-state and dynamic IR-drop. This turns power integrity from a late, manual sign-off step into a deterministic, CI-gated check.

In → out

design + PDN + IR/EM budget  ──►  vyges-em-ir  ──►  IR-drop map + EM check

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom em-ir

License

Apache-2.0

Used by: teams enforcing power budgets before tape-out, not after surprises.

On-chip thermal sign-off — the peak temperature and the hotspot from the same power map, with electro-thermal coupling. Analog and mixed-signal blocks too — heat flow is technology-agnostic.

What it does

vyges-thermal takes the design's floorplan power map — the per-instance power vyges-power already produces — and solves the die's heat flow: where the heat concentrates, the peak temperature, and the hotspot location, with a PASS/FAIL against a temperature limit. It is the thermal dual of vyges-em-ir: the same grid solve, temperature where em-ir has voltage. And because leakage rises with temperature, it runs the electro-thermal loop to a fixed point — leakage heats the die, the hotter die leaks more — so you get the real operating temperature, not a cold-start estimate. This turns thermal from a late packaging surprise into a deterministic, CI-gated check.

In → out

floorplan + power map + temp limit  ──►  vyges-thermal  ──►  temperature field + hotspot

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom thermal

License

Apache-2.0

Used by: teams that want to find the hotspot before the package does.

Geometric design-rule check — does the layout obey the foundry's rules? Width, spacing, area, density, antenna and enclosure on a GDS or OASIS layout — plus a metal-fill generator. Digital, analog and mixed-signal alike — geometry is technology-agnostic.

What it does

A layout is only manufacturable if its geometry obeys the foundry's rules. vyges-drc is the geometric sibling of lvs — LVS asks does the layout implement the schematic?, DRC asks does it obey the rules? It checks six rule classes — width, spacing, area, windowed density, per-net antenna ratio, and enclosure — and, where a layer is too sparse, it generates metal fill to hit the density target and writes a filled GDS back out. It rides the same clean-room vyges-layout kernel vyges-lvs uses, so the physical-verification pair is one toolset, one language, one install.

In → out

GDS + a .drc rule deck  ──►  vyges-drc  ──►  violations (text / JSON, CI exit code)

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom drc

License

Apache-2.0

Used by: anyone taping out — and anyone who wants the geometry checked in seconds inside CI, not in a six-figure tool.

Layout-vs-schematic — does the layout implement the schematic? A MATCH / MISMATCH verdict with diagnostics that name where it diverges. Digital, analog and mixed-signal netlists alike — the device-graph compare is technology-agnostic.

What it does

A layout is only correct if it implements the schematic — same devices, same connectivity. vyges-lvs proves that by matching the two netlists as graphs, independent of how nets and instances happen to be named (name-independent colour-refinement). When they don't match, the only thing that matters is where — so it names the unmatched devices and nets, where the open incumbent (Netgen) prints a terse "do not match." It can also extract the layout netlist straight from GDS, so you don't need a separate extractor in the loop.

In → out

layout netlist (or GDS + rules) + schematic  ──►  vyges-lvs  ──►  MATCH / MISMATCH + diagnostics

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom lvs

License

Apache-2.0

Used by: anyone signing off a layout — and anyone who has lost an afternoon to a cryptic mismatch report.

The design database, and the chiplet assembly layer on top of it — read a 2.5D/3D assembly, check its structure, check that its die-to-die interfaces actually connect, and draw it. One binary, no GUI, no Tcl.

What it does

vyges-opendb is a safe Rust API and CLI over OpenROAD's OpenDB — the in-memory design database that physical steps read and edit. It sits a layer below the sign-off engines: not an analysis, but the design data an analysis operates on. The division of labour is simple: OpenDB provides the data model; Vyges Loom provides the executable workflows built on that model.

In → out

3Dblox assembly  ──►  vyges-opendb  ──►  structural verdict + interface verdict + a drawing

Run it

Install

vyges install loom — with the Loom suite

Command

vyges opendb

License

Apache-2.0

Used by: anyone building a multi-die product, and any step that needs to read or edit a placed design directly.

Timing constraints you can trust — the SDC every stage of the flow times against, read once, checked, and written back the same way every time.

What it does

Every timing result in the flow is only as good as the constraints behind it, and a wrong constraint does not produce a wrong-looking report: it produces a clean one. vyges-sdc reads SDC into the same constraint model the Loom timer uses, so the checker and the timer always agree about what a file says. It checks the constraints against the design — coverage, consistency, and the clock domains an IP declares — and writes them back in one canonical form. Nothing is dropped silently: anything it does not carry is listed by name, never guessed at.

In → out

.sdc + netlist + .lib  ──►  vyges-sdc  ──►  findings · coverage · canonical .sdc

Run it

Install

vyges install physical — with the physical engines

Command

vyges physical sdc

License

Apache-2.0

Used by: anyone who writes or inherits an SDC — for a new block, an integrated IP, or a flow handed from one tool to the next — and needs to know the constraints mean what they say.

Gate sizing — pick a better drive strength for each cell to close setup timing or recover area. Where sign-off says what's wrong, this fixes it.

What it does

vyges-resize reads a netlist + Liberty + constraints and picks a better drive strength for each cell — upsizing cells on the critical path to close setup violations, downsizing cells with slack to recover area — then emits the resized netlist and a before/after timing report. The logic never changes; only the cell variant does. Every candidate is scored by the vyges-sta-si timer — it's pure Rust, so you can experiment with GPUs too via rust-gpu. It picks sizes, not locations: placement and routing stay the flow's job.

In → out

netlist + .lib + constraints  ──►  vyges-resize  ──►  resized netlist + before/after timing

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom resize

License

Apache-2.0

Used by: anyone closing timing on a synthesized or placed netlist — or trimming area/power once it's met.

Threshold-voltage swapping — trade a cell for a higher- or lower-Vt flavor of the same footprint to cut leakage while holding timing, or to close setup.

What it does

A higher-Vt flavor of a gate is slower but leaks far less; a lower-Vt flavor is faster but leakier. vyges-vt-swap is the sibling of vyges-resize — same idea, same timer-scored loop, but it trades threshold voltage (leakage/speed) rather than drive strength (area/speed). Two objectives, the inverse of each other:

In → out

netlist + .lib + constraints  ──►  vyges-vt-swap  ──►  resized netlist + before/after timing & leakage

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom vt-swap

License

Apache-2.0

Used by: anyone with leakage budget to recover after timing closes — or a few stubborn paths to speed up.

Buffer insertion — when a net is so heavily loaded its driver's transition blows past the limit, split it: a fresh buffer takes over a share of the sinks so the driver switches faster.

What it does

The third of the Loom optimizers, after resize and vt-swap. Those swap a cell for one with the same footprint; this one adds cells. vyges-buffer-insert finds the driver whose output transition most exceeds the limit, splits its net (a fresh buffer drives half the sinks, the driver keeps the rest), rebuilds the timer on the mutated netlist, and keeps the insertion if the worst transition dropped without breaking setup — repeating until every net is under the limit.

In → out

netlist + .lib + constraints  ──►  vyges-buffer-insert  ──►  buffered netlist + before/after slew & timing

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom buffer-insert

License

Apache-2.0

Used by: anyone chasing a max-transition / slew violation on a high-fanout net.

Post-route hold-fix ECO — data reaching a capture flop too early? Insert a delay cell in series on the offending pin, deepening a chain only where hold stays negative, until the hold constraint is met.

What it does

The hold counterpart to resize, vt-swap and buffer-insert — all of which fix the late / setup corner. Hold is the opposite problem: data arrives at a capture flop too early on the min-delay path. vyges-hold-fix reads the timer's per-endpoint hold slacks, inserts a delay cell in series on each hold-violating capture pin, grows a delay chain only where hold stays negative, and keeps a move only if the worst hold slack improved without pushing setup negative — so a slow clock's ample setup slack pays for hold closure, never the reverse.

In → out

routed netlist + .lib + .spef + constraints  ──►  vyges-hold-fix  ──►  hold-fixed netlist + before/after WHS & WNS

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom hold-fix

License

Apache-2.0

Used by: anyone left with hold violations after detailed routing — the ones the setup-side ECOs can't touch.

Clock-domain-crossing check — the metastability bug a simulator can't see. Find every signal that crosses between unrelated clocks without a synchronizer, named and located.

What it does

When a signal launched on one clock is captured by a flop on an unrelated clock, the capture can go metastable. That failure is invisible to a lockstep gate-level simulator — it samples one settled value per tick. Catching it is a purely structural graph question: vyges-cdc assigns each flop a clock domain by tracing its clock pin back to an SDC clock source, walks each capture flop's data cone to the flops that launch it, and reports every cross-domain crossing — flagging the ones that aren't a clean synchronizer.

In → out

netlist + .lib + .sdc  ──►  vyges-cdc  ──►  crossings (OK / unsynchronized), CI exit code

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom cdc

License

Apache-2.0

Used by: anyone integrating IP across multiple clocks — where the bug shows up in silicon, not in the testbench.

Static glitch / hazard analysis — find where a signal can momentarily glitch before it settles. The reconvergent-fanout hazard a cycle-based simulator steps right over.

What it does

When one signal reaches a gate's output by more than one path, those paths can disagree for a moment — and the output glitches before it settles. That is exactly what a lockstep gate-level simulator cannot see: it samples one settled value per tick and steps over the intermediate glitch. vyges-glitch catches it as a structural + timing question — it traces reconvergent fan-out and classifies each hazard static (paths of differing inversion parity) or dynamic (same parity, a delay-skewed settling window).

In → out

netlist + .lib  ──►  vyges-glitch  ──►  hazards (static / dynamic, with the window), CI exit code

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom glitch

License

Apache-2.0

Used by: anyone whose design feeds an async path, a latch, or a clock gate — where a transient glitch becomes a real bug.

Standard-cell characterization — generate Liberty (.lib) timing & power models from SPICE, in parallel, from one declarative job.

What it does

vyges-char takes SPICE models and a cell list and produces a Liberty library — the timing and power model every downstream sign-off step (STA, power) depends on. It orchestrates the underlying SPICE runs in parallel, which is the piece the open-source flow has historically lacked; it is validated against reference Liberty for the open PDKs. The emitted Liberty is standard Liberty that downstream sign-off tools consume directly, and supports multi-corner, multi-voltage characterization.

In → out

SPICE models + cell list  ──►  vyges-char  ──►  .lib (Liberty timing & power)

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom char

License

Apache-2.0

Used by: PDK teams, standard-cell library developers, and platform teams validating reusable IP.

Analog measurement you can defend — SNR, SINAD, THD, SFDR from a captured tone; gain, bandwidth, unity-gain frequency and phase margin from a sweep. Every number states the method that produced it, and refuses the inputs it cannot measure that way.

What it does

“SNR” on its own is not a measurement. The same capture, measured by two honest tools, can differ by several dB purely on convention: whether the fundamental bin is excluded from noise, how many harmonics are counted, whether DC is in the band, what happens to a harmonic that aliases onto another. vyges-meas does not implement “SNR” — it implements one closed method, states every choice it makes, and refuses a capture it cannot measure that way rather than returning a number that quietly means something else.

In → out

captured tone / AC sweep  ──►  vyges-meas  ──►  SNR · SINAD · THD · SFDR · gain · BW · phase margin

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom meas

License

Apache-2.0

Used by: anyone signing off an ADC, DAC, PLL or amplifier from simulation or bench data — where the number goes in a datasheet and has to survive review.

Headless GDS / OASIS layout viewer — render a layout to a layered SVG and overlay exactly where DRC or LVS flagged a problem. The where to the what, in any browser, no GUI to install.

What it does

drc and lvs tell you what is wrong with a layout. They don't show you where. vyges-gds-view closes that loop: render the GDS to a single self-contained SVG — every shape coloured by its layer, a legend, the Y axis the right way up — and drop the violation coordinates on top. Open it in any browser, commit it to a report, or diff it in CI. No display server, no GUI toolkit.

In → out

GDS (+ violation marks)  ──►  vyges-gds-view  ──►  a layered SVG with the overlay

Run it

Install

vyges install loom — with the Loom suite

Command

vyges loom gds-view

License

Apache-2.0

Used by: anyone debugging a DRC/LVS failure in CI — where you need to see the spot, not just read a coordinate.