Vyges Loom
Clock-domain-crossing check — the metastability bug a simulator can't see. Find every signal that crosses between unrelated clocks without a synchronizer, named and located.
Used by: anyone integrating IP across multiple clocks — where the bug shows up in silicon, not in the testbench.
When a signal launched on one clock is captured by a flop on an unrelated clock, the capture can go metastable. That failure is invisible to a lockstep gate-level simulator — it samples one settled value per tick. Catching it is a purely structural graph question: vyges-cdc assigns each flop a clock domain by tracing its clock pin back to an SDC clock source, walks each capture flop's data cone to the flops that launch it, and reports every cross-domain crossing — flagging the ones that aren't a clean synchronizer.
.lib + .sdc ──► vyges-cdc ──► crossings (OK / unsynchronized), CI exit code
Each create_clock in the SDC is a domain; the Liberty identifies the flops and their clock/data pins. A crossing is reported OK when it lands in a clean two-flop synchronizer, and a violation when there's no synchronizer — or when combinational logic sits on the crossing path, which a synchronizer must not have.
It complements your simulator instead of competing with it: it surfaces exactly the failure class a cycle-based run steps over. Reads the same Liberty / Verilog / SDC the rest of Loom does.
A clean-room Rust engine, runnable today, on the same shared netlist / Liberty / SDC parsers as the rest of the suite. See all the engines & the data spine →