Vyges Loom
Interconnect parasitic extraction — turn a layout's RC into SPEF, from one declarative job, so timing and power see the real wires. Analog and mixed-signal layouts too — RC is geometry, not cell-specific.
Used by: physical-design flows that want timing and power to see real wires — not estimates.
vyges-extract reads a layout and the PDK's parasitic rules and produces SPEF — the resistance and capacitance of every net. That's what lets static timing and power analysis reason about the actual interconnect, not an idealized one. SPEF is the standard hand-off the downstream engines expect. Extraction accuracy is governed by the PDK's parasitic rules — the engine is open, the calibration is foundry-specific; it handles hierarchical, full-chip designs.
An .ext job file declares the design, the PDK collateral, and the extraction settings. Standard CLI: --json, --quiet, --verbose. The .spef it emits is read directly by vyges-sta-si — one cross-engine data spine, no manual file shuffling.
One declarative job in; one standard sign-off artifact out. Exits non-zero on violations — designed to gate CI, not generate PDFs.
Open and runnable today, and inside VyBox Sley. The per-foundry calibration plugins (NDA) stay private. See all the engines & the data spine →