Vyges Loom
Static glitch / hazard analysis — find where a signal can momentarily glitch before it settles. The reconvergent-fanout hazard a cycle-based simulator steps right over.
Used by: anyone whose design feeds an async path, a latch, or a clock gate — where a transient glitch becomes a real bug.
When one signal reaches a gate's output by more than one path, those paths can disagree for a moment — and the output glitches before it settles. That is exactly what a lockstep gate-level simulator cannot see: it samples one settled value per tick and steps over the intermediate glitch. vyges-glitch catches it as a structural + timing question — it traces reconvergent fan-out and classifies each hazard static (paths of differing inversion parity) or dynamic (same parity, a delay-skewed settling window).
.lib ──► vyges-glitch ──► hazards (static / dynamic, with the window), CI exit code
Parity comes from each Liberty arc's unateness; the glitch window comes from the same delay tables sta-si times with. The analysis is a memoized traversal — polynomial in the design, never an exponential path walk — that finds the structural opportunity for a glitch a simulator is blind to.
A clean complement to the simulators it's invisible to — on the same timing data your sign-off already produces.
A clean-room Rust engine, runnable today, reading the same Liberty and netlists the rest of Loom does. See all the engines & the data spine →