Vyges Loom

vyges-remap

Multi-output technology re-mapping — recovers the area a one-output-at-a-time mapper leaves behind, and proves the function did not change before it hands the netlist on.

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What it does

Used by: anyone whose block is over its area budget after synthesis — particularly datapath, where the shared structure is the whole point.

A conventional technology mapper covers one output at a time, so a cell that could have driven several outputs gets duplicated once per output. In arithmetic and datapath logic, where sub-expressions are shared everywhere, that duplication is a standing area tax. vyges-remap re-maps the same logic with a multi-output covering, then reports the before/after cell and area delta against a single-output baseline it computes itself — so the gain is measured, not asserted.

mapped netlist  ──►  vyges-remap  ──►  smaller netlist + measured delta, equivalence-checked

An optimizer that has to prove itself

Area is easy to win by accident and expensive to lose by accident. So a re-map is not trusted because the algorithm is sound — it is combinationally equivalence-checked against the input, and a re-map that changed the function is reported as such rather than written out. This is the same rule the rest of the suite runs on: the optimizers score every move against sta-si, and this one scores itself against a checker.

It sits upstream of placement, at the logic level, where structural area is still cheap to change — the complement to the physical-side optimizers that work after the netlist is committed to a floorplan.

Fewer cells before placement is smaller die, shorter wires, and less for every downstream engine to analyze.

Try it

Bring your own logic tools. Unlike the rest of Loom, this engine is a driver: the mapping itself is done by mockturtle's emap, AIG extraction by Yosys, and the equivalence check by ABC. Point $VYGES_EMAP, $VYGES_YOSYS and $VYGES_ABC at your builds — vyges install loom does not supply them, and vyges-remap will tell you which one it could not find rather than proceeding without it.

$ vyges install loom   # one-time: fetch the Loom suite into ~/.vyges/bin
$ export VYGES_EMAP=/path/to/emap VYGES_YOSYS=$(which yosys) VYGES_ABC=$(which abc)
$ vyges loom remap emap --verilog block.v --top block --liberty sky130.lib -o block_remapped.v
$ vyges loom remap emap --aig block.aig --genlib cells.genlib --json   # machine payload

The equivalence check runs by default; --no-cec skips it, and says so in the result.

Open core · Apache-2.0

A Rust driver over open logic-synthesis research, wearing the same result envelope as every other engine. See all the engines & the data spine →