IP Template Generator

Instantly scaffold IP repositories with best-practice templates for ASIC and FPGA

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Standardized IP Templates

Everything you need to create production-grade IP — from RTL and testbenches to documentation and build flows. Pre-configured, standards-aligned, and ready to go.

Pre-configured Structure

Organized folder structure including RTL, testbenches, documentation, flows, and scripts — out of the box

Metadata Integration

Built-in support for Vyges metadata — auto-generated and schema-validated

Multi-Platform Support

Optimized for both ASIC and FPGA flows — choose your path and start building

Ready to Start?

Create your first IP repository with our template generator

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Template Features

Documentation Ready

Comes with ready-to-edit README, architecture diagrams, and API documentation templates

Testing Framework

Supports UVM, Cocotb, and SystemVerilog — verification built into the template

CI/CD Integration

GitHub Actions templates for validation, linting, simulation, and publishing

Explore the Template Layout

Fully Organized Directory Layout

📁 your-ip-name/
├── 📁 rtl/
├── your_block_your_module.sv
└── your_block_your_core.sv
├── 📁 tb/
├── 📁 sv_tb/
└── 📁 cocotb/
├── 📁 docs/
├── architecture.md
└── api_reference.md
├── 📁 flow/
├── 📁 openlane/
└── 📁 vivado/
├── 📁 scripts/
├── 📁 test/
├── 📁 integration/
└── your_block_your_wrapper.v
├── 📁 constraints/
├── constraints.sdc
└── constraints.xdc
├── 📁 packaging/
├── 📁 layout/
├── 📁 simulation/
├── 📁 analog/
├── 📄 README.md
├── 📄 vyges-metadata.json
├── 📄 .vyges-ai-context.json
├── 📄 LICENSE
└── 📄 .gitignore

Key Components

RTL Design

Clean, modular SystemVerilog with reusable interfaces and parameters. Follows Vyges naming convention: {block}_{module}.sv

Test Infrastructure

Mixed-method testbenches — Cocotb, UVM, and functional simulation

Build Flows

Synthesis and implementation flows for OpenLane and more

Documentation

Markdown-based docs that align with your metadata and CI reporting

Metadata & AI Context

JSON-based Vyges metadata with AI context engine support — schema-enforced, CI-integrated, and automation-ready

Why Use Vyges IP Templates?

Saves Hours of Setup

Skip boilerplate setup — start coding with a complete, ready-to-use structure

Enforces Structure

Enforces standards and best practices for clean, maintainable IP

Academic & Production

Ideal for both academic exploration and production-grade development

Scales with Teams

From solo developers to enterprise teams — scales with your project

Simple Development Workflow

From Template to Production in Minutes

Our streamlined workflow makes IP development accessible to everyone. Start with our template, choose your development environment, and build production-ready silicon IP with AI assistance.

1
Create repository from GitHub template (vyges-ip-template)
2
Choose local development or VyBox Lite on GitHub Codespaces
3
Develop with AI-assisted design & verification
4
Generate RTL, testbench, docs, synthesis & reports
🌐 Vyges-IP-Template Create Repository Choose Mode Local Development VyBox Lite Codespaces Develop Silicon IP AI-Assisted Design 📊 RTL, Testbench, Docs, Synthesis, Reports

Use Cases

ASIC Development

Build silicon-ready IPs with full-stack flows for synthesis, verification, and timing

  • • OpenLane P&R and synthesis integration
  • • DRC and LVS checks built into flows
  • • Static timing with clock and constraint coverage
  • • Power reporting and optimization scaffolds

FPGA Development

Generate FPGA-targeted IP with vendor-ready flows and board-specific examples

  • • Common EDA tool project templates
  • • Pre-filled SDC/XDC constraints
  • • Auto-packaging for IP cores
  • • Integration hooks for dev boards and test apps

Ready to Create Your First IP?

Spin up your IP project in seconds — complete with metadata, structure, tests, and docs.

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