Free Tools

Browser-based tools for silicon IP and chip design — no login, no license, no install.

Small, focused tools that solve one problem well. Built in the open, free to use, and part of how we ship AI-native silicon engineering.

Available now

Everything here runs free in your browser.

In development

Tools we're building next. Want one sooner? Tell us.

Coming soon

Tape-out Cost Estimator

Sketch a die size and PDK, get a ballpark MPW shuttle estimate before you commit.

Coming soon

Register-Map Generator

Describe a peripheral's registers and export clean docs and RTL stubs.

Coming soon

Liberty & SPEF Viewer

Drop in a .lib or SPEF file and inspect timing arcs and parasitics in the browser.

Free · one binary

Prefer the terminal? Get the Vyges CLI

The Vyges CLI is the command-line front door — like npm or pip for silicon. Find & fetch verified IP from the catalog (vyges catalog), resolve & install PDK collateral (vyges pdk-store), and add the sign-off engines with vyges install loom. Free, Rust, --json on every command.

Open-source · Apache-2.0

Looking for the sign-off engines?

The browser tools above are the front door. Vyges Loom is the full suite of commercial-grade EDA sign-off engines — timing with signal integrity, parasitic extraction, power, EM/IR, thermal, LVS, and the optimizers that close the loop. Free and open, installed via the CLI (vyges install loom), driven by declarative job files, CI-native — and drivable by any AI model locally through vyges mcp.

Build with the full platform

These tools are the front door. The CLI, registry, and open EDA sign-off engines are where teams ship real silicon.

Questions, or found a bug? Join the discussion on GitHub →