Vyges Loom
Find antenna violations before they become silicon failures.
Check the routed database and get the exact gate and layer for every violation — including where the protection diode needs to go.
Used by: anyone taking a routed block to a foundry — antenna damage passes every simulation, survives every functional test, and turns up as yield loss.
During fabrication, a long run of metal connected to a transistor gate acts as an antenna: it collects charge from the plasma etch and dumps it through the thin gate oxide. Too much metal per unit of gate area and the oxide is damaged — a device that passes every simulation and fails in silicon. The foundry states the limit as a set of ratios in the LEF, and the layout has to stay under them.
vyges-ant checks them on the routed design database — all four forms (PAR, CAR, PSR, CSR), plain and diffusion-dependent, stage by stage as the metal stack is deposited. It does not just say a net failed: it names the gate, the layer, the value and the limit it broke.
.odb ──► vyges-ant ──► antenna violations (gate · layer · value vs limit), CI exit code
"Net n1234 failed" does not tell you what to do. A protection diode goes on a specific gate, and the metal that damaged it was collected on a specific layer — so that is what the report names, along with the value and the limit it broke.
That precision comes from charging metal to the gates on that piece of metal, rather than pooling a whole net together. Simpler models are why a checker either buries you in violations that are not real or, worse, hides ones that are.
And when you disagree with the verdict, explain shows the working — gate by gate, stage by stage — instead of asking you to trust it.
Foundries state antenna limits two different ways: as a constant per layer, or as a curve that rises with the diffusion connected to the net — which is exactly how a protection diode earns relief. A checker that reads only the first finds nothing at all on a technology that uses only the second, and reports a clean run.
That is not hypothetical: sky130 states only the diffusion-dependent form. vyges-ant reads both. And where a technology states no limit for a ratio, it says so in the report rather than letting a clean verdict imply a check that never ran.
It is cross-checked net-by-net against OpenROAD's check_antennas — agreeing on the net, the pin, the layer and the ratio — so you get a second opinion from a different implementation, in seconds, in CI. Keep check_antennas for sign-off; use this to stop shipping a block to it that was never going to pass.
Exit status is the verdict: 0 clean · 1 violations · 2 error — so CI gates on the exit code without parsing prose.
Timing is the whole point. Antenna is created by routing, and the routed database is the last stage where a violation is still cheap to fix — you insert a diode and re-route. Find it after stream-out and the answer arrives too late to act on. vyges-ant reads that database through vyges-opendb, so it runs where the fix still exists.
It is the routing-stage counterpart to vyges-drc, which checks antenna geometry post-stream on a GDS. Same physical rule, two different stages — and the earlier one is the one you can still act on.
A clean-room Rust engine over the routed design database, reading the same foundry LEF rules the rest of the flow does. See all the engines & the data spine →