Vyges Loom
Geometric design-rule check — does the layout obey the foundry's rules? Width, spacing, area, density, antenna and enclosure on a GDS — plus a metal-fill generator. Digital, analog and mixed-signal alike — geometry is technology-agnostic.
Used by: anyone taping out — and anyone who wants the geometry checked in seconds inside CI, not in a six-figure tool.
A layout is only manufacturable if its geometry obeys the foundry's rules. vyges-drc is the geometric sibling of lvs — LVS asks does the layout implement the schematic?, DRC asks does it obey the rules? It checks six rule classes — width, spacing, area, windowed density, per-net antenna ratio, and enclosure — and, where a layer is too sparse, it generates metal fill to hit the density target and writes a filled GDS back out. It rides the same clean-room vyges-layout kernel vyges-lvs uses, so the physical-verification pair is one toolset, one language, one install.
.drc rule deck ──► vyges-drc ──► violations (text / JSON, CI exit code)
A small whitespace rule deck keyed on the GDS layer number — readable, diffable, schema-checkable — instead of a tool-specific rule language:
width 66 170 # min width on layer 66 space 68 140 # min spacing area 68 20000 # min polygon area density 68 20 70 100000 # coverage 20–70% per window connect 5 68 # layers connect where they overlap (via) antenna 68 5 400 # per net: conductor area ≤ 400 × gate area enclosure 68 66 40 # layer-66 shapes enclosed by layer-68 ≥ 40 fill 70 30 100000 600 400 # generate fill: top layer 70 to 30%
Antenna and enclosure bring connectivity and cross-layer checks, not just per-shape geometry. The reference deck ships for the open PDKs; the certified per-foundry deck stays private under the foundry's terms.
The geometry engine is open and runnable today, with no foundry-confidential data — the rule deck is the plugin boundary. An open reference deck ships for the open PDKs; a certified per-foundry deck stays private. See all the engines & the data spine →