Vyges Loom · Physical implementation
Find every clock, choose its buffers, and collect every sink it has to reach.
Buffer inference from your libraries, clock-gate cloning, and clock nets traced through gaters and pads.
Used by: anyone with a clocked design — which is every design; the clock network is where skew, power and hold all begin.
Before a clock tree can be built, the tool has to know what it is building with and what it has to reach. Which buffers may drive a clock? Which nets are clocks at all, once they pass through clock gates and bidirectional pads? Which flip-flops sit at the end of each one?
vyges-cts infers the buffer list from your libraries (or takes the one you give it), selects the root, sink and characterization buffers, clones clock gates, and traces every clock net to its sinks — through gaters and bidirectional pads — reporting each in the order the synthesis meets it.
.odb + Liberty + SDC + JSON job ──► vyges-cts ──► clock nets, sinks and buffer choices (JSON)
Buffer selection follows the library: dont-use cells are respected, wire and layer RC come from the job, and the choice of root and sink buffer is reported with the cells it chose between.
Clock discovery follows the netlist, not the net names: a clock is whatever the constraints say it is, traced through every gate and pad it actually passes.
The report's lines come out in the order synthesis produces them, so it lines up with a log you already know how to read.
Status is up to date, vacuous or error. Up to date means the clock nets were looked for and none needs a tree; vacuous means the job never asked, and it is not a pass.
Exit status is the verdict: 0 up to date · 2 vacuous or error.
A clean-room Rust engine working on the shared design database through vyges-opendb, so the block you check is the block you built. See all the engines & the data spine →