Vyges Loom · Physical construction
Build the power grid — and refuse the one the technology cannot hold.
Rings, straps, follow pins and the vias that stitch them together, published as block terminals the next tool can actually find.
Used by: anyone who needs power to reach the cells — and anyone who has debugged a grid that looked fine until the via stage.
The power distribution network is the structure everything else sits inside. It is built from a small vocabulary — rings around the core, straps across it, follow pins along the standard-cell rows — and then vias connect the layers wherever those shapes cross.
vyges-pdn builds all four, on the shared design database, and publishes each supply net as a block terminal so the next tool in the flow can find the grid rather than infer it.
.odb + grid spec (rings, straps, follow pins) ──► vyges-pdn ──► grid shapes, vias, block terminals
Most of the cost of a power grid is discovering, late, that some part of it was never legal. So the checks run first: a strap that cannot snap to the routing tracks or fit its grid is refused; a connect rule that names one layer twice, or names a layer that is not a routing layer, is refused — by name, with the rule that rejected it.
Spacing derived from the technology is snapped to the manufacturing grid, not left on an off-grid fraction that fails much later in a DRC deck.
Via arrays widen their cut pitch where ADJACENTCUTS applies, and a via built once is reused for every crossing of the same size — the geometry is built after trimming, the way the database expects to receive it.
A grid that is subtly wrong does not announce itself. It survives generation, survives the via stage, and turns up much later as a DRC deck full of noise or a block that will not route — by which point the cheap fix is hours behind you.
So this refuses up front, by name: the strap that cannot snap to tracks, the connect rule naming a layer that is not a routing layer, the dimensions the layer will not allow. You get the rule that rejected it and what it wanted — a message you act on in a minute, not a symptom you spend an afternoon tracing back.
And it runs in seconds from one binary, so trying three grid styles before lunch is a normal afternoon rather than a scheduling decision. (One thing worth knowing if you diff this against another tool: shapes are emitted before trimming, which belongs with the via stage — skip trimming on the other side and you are comparing like with like.)
Emits the grid as DEF plus a JSON report on stdout, and exits non-zero on a refusal — so CI gates on the exit code without parsing prose.
After vyges-ifp and vyges-tap — follow pins run along the rows, so the rows have to exist and be cut first. The grid it builds is what vyges-em-ir later analyses for IR drop and electromigration: the same database, built and checked by the same suite.
A clean-room Rust engine writing the shared design database through vyges-opendb, so the block you check is the block you built. See all the engines & the data spine →