Vyges Loom · Physical implementation
The shape of every net, before it is routed.
Rectilinear Steiner minimal trees over a net's pins — the starting point for parasitic estimation, repair and routing.
Used by: every engine that needs to know how a net will be wired before it is — estimation, repair and global routing all start here.
Before a net is routed, its wiring is a guess — and the quality of that guess decides how good every estimate built on it can be. The standard guess is a rectilinear Steiner minimal tree: the shortest set of horizontal and vertical wires that connects all of a net's pins.
vyges-stt builds it two ways: a fast table-driven construction tuned for the small nets that make up most of a design, and Prim–Dijkstra, which trades total wirelength against source-to-sink path length — the knob that matters for timing-critical nets.
run builds one tree; batch builds a tree for every net in a file; check verifies a tree you already have for self-overlap. Each answers in JSON, or in the printed tree format your existing flow expects.
The same library is what est, rsz and grt build on — so the tree you inspect is exactly the tree they use.
A tree that overlaps itself is reported as a finding with its own exit code, not passed downstream.
Status is ok, failed, vacuous or error. A net with no pins — or a batch of none — is vacuous: nothing was built, and it is not a pass.
Exit status is the verdict: 0 ok · 1 the tree failed its self-overlap check · 2 vacuous or error.
A clean-room Rust engine working on the shared design database through vyges-opendb, so the block you check is the block you built. See all the engines & the data spine →