Vyges Loom · Physical implementation
Every net's RC, from placement — without waiting for the router.
A Steiner tree per net, its RC network per corner, written as SPEF any timer reads.
Used by: anyone timing a placed design — placement-stage timing is only as good as its parasitic estimate.
Timing a placed design needs the resistance and capacitance of wires that do not exist yet. Parasitic estimation fills that gap: it predicts each net's wiring and turns the prediction into an RC network the timer can use.
vyges-est builds a Steiner tree per net with stt, converts it to an RC network per corner using your layer and wire RC, and writes it as SPEF — the same format sta-si reads from a fully extracted design.
.odb / LEF + DEF + Liberty + JSON job ──► vyges-est ──► .spef per corner
Because the output is plain SPEF, there is nothing special about using it: the timer that reads the post-route extraction reads the placement estimate the same way. Move from one to the other and only the numbers change.
Multiple corners, propagated clocks and per-layer RC are all part of the job; a trace writes the RC state and one decision line per net, so an estimate you doubt is one you can read.
The Prim–Dijkstra trade-off is a job setting, so the tree shape behind every estimate is something you choose.
Status is estimated, vacuous or error. If no net was estimated — no estimate step, or no corner with wire capacitance — the run is vacuous and not a pass, rather than a SPEF full of zeros.
Exit status is the verdict: 0 estimated · 2 vacuous or error.
A clean-room Rust engine working on the shared design database through vyges-opendb, so the block you check is the block you built. See all the engines & the data spine →