Most AI can talk about a failing timing report. Vyges lets a model fix it — driving real optimizers and sign-off engines until the design is green.
The AI proposes; deterministic engines do the work and score every move.
A model reads the verdict, proposes a change, a deterministic engine applies it, and the result is re-scored — repeat until it's green. loom.feedback gives the agent its eyes: one call returns a rendered layout, categorized verdicts, and a score — so an agent can debug a design, not just pass/fail it.
read the verdict → propose a fix → engine applies it → re-score → green?
▲ │
└──────────────────────────── not yet ───────────────────────────────┘
Every move is scored by the same sta-si timer that signs the design off — so a "fix" that breaks something else can't slip through.
Each fix is a real Engineering Change Order (ECO) — a targeted, incremental netlist edit — from a Loom optimizer, scored against the same sign-off.
Pick a better drive strength per cell — upsize the critical path to close setup, downsize slack for area. Pre-place or post-place ECO with SPEF.
Trade threshold voltage iso-footprint: high-Vt to cut leakage where there's slack, low-Vt to close setup.
Split a heavily-loaded net so the driver's transition drops back under the limit, timing still met.
Insert series delay on hold-violating capture pins, scored against real routed parasitics.
Categorized DRC verdicts + a rendered overlay via loom.feedback — the agent sees where and iterates, plus metal-fill to hit density.
A name-independent graph match returns MATCH/MISMATCH with the divergence named — the agent knows exactly what to reconcile.
vyges mcp — your design never leaves the building.This is where AI has immediate, demonstrable value in silicon: not writing prose about a report, but closing the loop on a real one.
Bring any model, run it locally, and let it fix — not just describe — your timing, power, and DRC.