Vyges Blog

Latest insights, updates, and technical content from the Vyges team

Discover how to build, test, and deploy reusable silicon IP with modern engineering practices.

Recent Posts

We Didn't Train the AI. We Taught Our Tools to Explain Themselves.

July 16, 2026 • By Shivaram Mysore

No fine-tuning, no orchestration code. We gave each of Vyges Loom's twenty-plus sign-off engines a clear, typed, machine-readable interface — and an off-the-shelf GPT-4.1 model, connected through MCP, discovered the tools and drove the sign-off flow on its own. Orchestration became a property of the interfaces, not the model — so today's model isn't special, and tomorrow's works too.

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How do I use a local SemiKong LLM to drive DRC sign-off?

July 9, 2026 • By Shivaram Mysore

A semiconductor LLM can reason about DRC — it can't run it. This walkthrough points a locally-hosted SemiKong at real DRC on your own hardware, with real captured output on a taped-out IP: the model proposes the tool call, the deterministic vyges-drc engine is the ground truth, and nothing leaves your machine.

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Timing Sign-Off for the Open Silicon Era — and Why We Wrote It in Rust

June 25, 2026 • By Shivaram Mysore

Open EDA gave the world synthesis, place-and-route, and DRC — but not commercial-grade timing sign-off. We built it: WNS/TNS with signal integrity, foundry-standard formats, CI-native. And we wrote it in Rust, so it runs natively everywhere from Apple Silicon to Arm64 cloud — with a parallel-by-design architecture that doesn't foreclose the GPU.

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