Latest insights, updates, and technical content from the Vyges team
Discover how to build, test, and deploy reusable silicon IP with modern engineering practices.
Getting a floorplan out of an open flow has meant installing the whole flow. We took the six steps that build one and shipped them as static binaries you can point at your own netlist. Four die sizes explored in under a minute — and on a block whose taped-out DEF we can check against, the rows and tracks match exactly.
Read more →Cloudflare and Spotify both shipped agent platforms this month, and each answers a different question about why an AI agent cannot be trusted to act on its own. There are three such questions — and almost nobody is working on the third.
Read more →One year ago today, Vyges launched with a claim: silicon should be built like software. A year on, the catalog is open, the sign-off engines are open, and a chip has gone from specification to tapeout using the foundation we set out to build.
Read more →Advanced packaging has been the part of silicon design that open tools could not reach. That changed. You can now describe a chiplet assembly, check that it is structurally sound, check that its die-to-die interfaces actually connect, draw it, and gate CI on all of it — with open-source tools, on your own machine.
Read more →Assembly description in, verdict and drawing out, with a CI gate at the end. The complete open chiplet flow in one page — plus the five-minute demo where a one-character change kills an entire die-to-die bus and the structural checks stay green.
Read more →Two chips bonded together are only connected if the bumps on their mating faces land on each other and carry the same signals. A one-character mistake left an entire 8-bit die-to-die bus connected to nothing — and every open-source structural check reported the assembly clean. So we built the check that catches it.
Read more →An assembly is not a design file — it is a description of how several dies are placed, flipped and bonded. OpenROAD's OpenDB made that describable in the open. Here is how to write one, check it, and draw it as a cross-section, from one command line with no GUI.
Read more →No fine-tuning, no orchestration code. We gave each of Vyges Loom's twenty-plus sign-off engines a clear, typed, machine-readable interface — and an off-the-shelf GPT-4.1 model, connected through MCP, discovered the tools and drove the sign-off flow on its own. Orchestration became a property of the interfaces, not the model — so today's model isn't special, and tomorrow's works too.
Read more →A semiconductor LLM can reason about DRC — it can't run it. This walkthrough points a locally-hosted SemiKong at real DRC on your own hardware, with real captured output on a taped-out IP: the model proposes the tool call, the deterministic vyges-drc engine is the ground truth, and nothing leaves your machine.
Install the Vyges Loom engines, run one command, and your AI IDE — Claude Code, Cursor, or VS Code — can drive real DRC, LVS, and timing sign-off on your own machine. No cloud. No upload. No auth. The engines stay deterministic; the agent just drives.
Read more →Open EDA gave the world synthesis, place-and-route, and DRC — but not commercial-grade timing sign-off. We built it: WNS/TNS with signal integrity, foundry-standard formats, CI-native. And we wrote it in Rust, so it runs natively everywhere from Apple Silicon to Arm64 cloud — with a parallel-by-design architecture that doesn't foreclose the GPU.
Read more →Software has PyPI, npm, and Crates.io. Until VyCatalog, silicon had nothing equivalent. 125+ open-source silicon IPs, machine-readable, free, and growing.
Read more →Introducing VyBox Lite — a browser-accessible development environment that brings the full power of silicon IP development to the cloud, complete with AI assistance and pre-configured EDA tools.
Read more →Learn how to create, test, and deploy reusable silicon IP blocks using Vyges. From template to working IP with AI assistance, CI/CD, and automated reporting.
Read more →Structured like software. Verified by automation. Reused with confidence. Vyges brings modern software engineering practices to silicon IP development.
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