Vyges Loom
On-chip thermal sign-off — the peak temperature and the hotspot from the same power map, with electro-thermal coupling. Analog and mixed-signal blocks too — heat flow is technology-agnostic.
Used by: teams that want to find the hotspot before the package does.
vyges-thermal takes the design's floorplan power map — the per-instance power vyges-power already produces — and solves the die's heat flow: where the heat concentrates, the peak temperature, and the hotspot location, with a PASS/FAIL against a temperature limit. It is the thermal dual of vyges-em-ir: the same grid solve, temperature where em-ir has voltage. And because leakage rises with temperature, it runs the electro-thermal loop to a fixed point — leakage heats the die, the hotter die leaks more — so you get the real operating temperature, not a cold-start estimate. This turns thermal from a late packaging surprise into a deterministic, CI-gated check.
That closes the power-integrity spine end to end: char → power → em-ir → thermal → power — one shared activity map, landed on the die as current and as heat.
A .thermal job declares the die, the grid, the material parameters, and the temperature limit; a .flp floorplan places the blocks and their power. Standard CLI: --json, --quiet, --verbose — and like the rest of the spine it can fail CI when the peak exceeds the limit.
One declarative job in; a temperature field, the hotspot, and a verdict out. Exits non-zero over the limit — designed to gate CI, not generate PDFs.
Open and runnable today, and inside VyBox Sley. The per-foundry/package calibration plugins (NDA) stay private. See all the engines & the data spine →